Senior STA Engineer

About this job

Astera Labs is a NASDAQ-listed company delivering rack-scale AI infrastructure through specialized connectivity solutions like CXL, Ethernet, NVLink, PCIe, and UALink combined with the COSMOS software suite. The company works closely with hyperscalers and ecosystem partners to build flexible, high-performance systems for modern AI. As a Senior STA Engineer based in Ahmedabad, you will play a crucial role in managing Static Timing Analysis, timing signoff, and timing closure for advanced ASIC and SoC designs. Your daily work involves running multi-corner multi-mode timing analysis, reviewing SDC constraints, debugging critical setup and hold violations, driving physical and logical timing closure, supporting ECO implementation, and collaborating closely with RTL, physical design, and synthesis teams to meet strict tape-out schedules.

Responsibilities

• Own full STA and timing signoff activities from synthesis to tape-out.
• Perform MCMM/MMMC timing analysis across various functional and test modes.
• Debug and resolve setup, hold, recovery, removal, and clock-related violations.
• Develop, review, and validate SDC constraints and timing exceptions.
• Drive timing closure by partnering with RTL, synthesis, and physical design teams.
• Execute timing analysis covering OCV/AOCV/POCV, crosstalk, and PVT variations.
• Support timing ECOs and create Tcl/Python scripts for STA automation.

Requirements

• 6+ years of experience in Static Timing Analysis and timing closure.
• Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
• Strong command over SDC constraints and timing exceptions.
• In-depth understanding of ASIC/SoC design and signoff flows.
• Familiarity with MCMM/MMMC analysis and variation-aware timing.
• Proficiency in Tcl scripting for automation and flow optimization.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.

Good to have

• Python or Perl scripting experience
• Experience mentoring junior engineers

Who should apply

This role is ideal for experienced semiconductor professionals with a strong background in static timing analysis, timing closure, and ASIC design flows. It suits engineers who enjoy solving complex timing problems, driving cross-functional collaboration, and mentoring junior team members. If you have the required hands-on tool experience and are ready to work in a fast-paced environment at Astera Labs, you should consider applying.

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