Principal Logic Design Engineer

About this job

Astera Labs is looking for a Principal Logic Design Engineer to join the team in Bengaluru, Karnataka, India. Astera Labs develops purpose-built connectivity solutions and rack-scale AI infrastructure, integrating semiconductor technologies with their COSMOS software suite to help organizations build efficient AI systems. In this role, you will take technical ownership of complex IPs and subsystems from architecture to silicon bring-up. A normal day in this position involves leading RTL and microarchitecture development, translating requirements into hardware architecture, designing high-performance logic, and optimizing for power, area, and latency. You will also collaborate with verification, SoC integration, and physical design teams, lead technical reviews, mentor senior engineers, and support post-silicon debug and root-cause analysis.

Responsibilities

• Lead RTL and microarchitecture development for complex connectivity IP and subsystems
• Translate system requirements and specifications into robust hardware architecture
• Design high-performance and scalable logic for controllers and subsystems
• Develop and review RTL using SystemVerilog and Verilog
• Drive performance, latency, area, and power optimization
• Collaborate with verification teams to shape strategies and debug failures
• Work alongside SoC integration and physical design teams for implementation
• Support post-silicon debug and root-cause analysis

Requirements

• Extensive experience in complex connectivity IPs like PCIe, UALink, Ethernet, CXL, or UCIe
• Strong RTL design experience using SystemVerilog or Verilog
• Deep knowledge of PCIe architecture and protocol
• Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling
• Experience with simulation, lint, CDC, synthesis, and timing considerations
• Strong problem-solving and debugging skills

Good to have

• Experience working in switching silicon
• Experience working on the entire cycle from concept to silicon production

Who should apply

This role suits experienced semiconductor professionals with a strong background in micro-architecture, RTL design, and complex connectivity IPs. Candidates should possess extensive industry experience and deep knowledge of protocols like PCIe. It is well-suited for senior engineers ready to provide technical leadership, mentor team members, and drive end-to-end silicon development at Astera Labs.

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