Silicon Design Architect

About this job

Astera Labs in Bengaluru is hiring a Silicon Design Architect to define the technical direction of complex semiconductor IPs and subsystems for rack-scale AI infrastructure. Astera Labs develops purpose-built connectivity solutions and its Intelligent Connectivity Platform integrates various semiconductor-based technologies with the COSMOS software suite to unify AI systems. In this role, you will own the architecture definition from early requirements through to implementation. A normal working day involves translating system needs into clear microarchitectures, evaluating performance and power trade-offs, writing technical specifications, and collaborating closely with SoC, RTL, verification, physical design, firmware, and system architecture teams to drive architectural solutions.

Responsibilities

• Define architecture and microarchitecture for complex IP blocks and SoC subsystems.
• Translate system requirements into detailed specifications, interfaces, and performance targets.
• Evaluate trade-offs regarding performance, power, area, latency, bandwidth, and scalability.
• Define protocols and interfaces such as PCIe, UALink, AXI, APB, and CHI.
• Create architecture specifications, block diagrams, and technical documentation.
• Partner with RTL, verification, physical design, DFT, firmware, and system teams.
• Review RTL and verification strategies to guarantee alignment with architectural goals.
• Provide technical leadership, mentorship, and drive architecture reviews with leadership.

Requirements

• Strong background in IP architecture and microarchitecture.
• Strong understanding of digital design, computer architecture, memory systems, and interconnects.
• Experience with high-speed interfaces and/or coherent interconnects.
• Strong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.
• Excellent technical communication and problem-solving skills.

Good to have

• Experience with PCIe, UALink, CXL, Ethernet, CCIX, or CHI technologies.
• Experience with AI/accelerator, networking, compute, or high-performance SoC architectures.
• Experience taking IP and subsystems from architecture through silicon production.
• Background in ASIC/SoC architecture and microarchitecture.

Who should apply

This role suits experienced semiconductor professionals with over 20 years of background in IP and subsystem architecture. It is ideal for candidates who possess deep knowledge of digital design, high-speed interfaces, and performance modeling, and who have a track record of driving technical decisions across cross-functional engineering teams. Freshers cannot apply as 20+ years of experience is required.

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