DFT Engineer

About this job

Astera Labs, a company focused on rack-scale AI infrastructure and connectivity solutions, is hiring for a DFT Engineer role based in Bengaluru, Karnataka. Astera Labs provides purpose-built semiconductor technologies integrated with the COSMOS software suite to help organizations unlock the potential of modern AI. In this role, you will be part of a team working on cutting-edge connectivity solutions that power large AI clusters. A normal day in this full-time position involves partnering across teams to take features from specification to silicon, working on complex blocks, contributing to design methodologies, and collaborating closely with architecture, verification, physical design, and DFT teams to ensure high-quality, scalable semiconductor products.

Responsibilities

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
• Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
• Partner with architecture to translate specifications into implementation-ready microarchitecture
• Collaborate with verification, DFT, and physical design teams on testplans, coverage closure, scan, BIST, floorplanning, and timing closure
• Mentor junior engineers and contribute to design methodology, scripts, and best practices
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of digital design experience, including at least one full chip from spec to tapeout
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques
• Solid understanding of high-speed serial interfaces like PCIe or Ethernet, and SoC integration

Good to have

• MS or PhD in Electrical Engineering or Computer Engineering
• Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
• Familiarity with formal verification, emulation, or assertion-based methodologies
• Background in advanced process nodes such as 7nm, 5nm, or below
• Strong debug skills across pre-silicon and post-silicon environments

Who should apply

This role suits experienced digital design professionals who have a solid background in semiconductor development, tapeout execution, and high-speed serial interfaces. Candidates should have at least five years of experience and a relevant engineering degree. It is ideal for engineers who thrive in a fast-paced, high-growth environment focused on AI infrastructure connectivity. Freshers should not apply as 5+ years of digital design experience is required.

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