Principal Logic Design Engineer - UALink IP/Subsystem
About this job
Astera Labs is seeking a Principal Logic Design Engineer for a full-time position in Bengaluru, Karnataka, India. The company builds rack-scale AI infrastructure through connectivity solutions that integrate technologies like CXL, Ethernet, NVLink, PCIe, and UALink to help organizations scale AI systems. In this role, you will be responsible for leading RTL and microarchitecture development for UALink IP and subsystems. A normal day in this position involves translating protocol and system requirements into hardware architecture, designing high-bandwidth data paths, writing and reviewing SystemVerilog RTL, optimizing designs for performance, power, area, and latency, and collaborating closely with cross-functional teams such as verification, physical design, and firmware. You will also debug complex simulation issues and provide technical leadership and mentorship within the team.
Responsibilities
- Lead architecture and RTL development for UALink IP/subsystems.
- Translate protocol and system requirements into scalable hardware architecture.
- Design high-bandwidth, low-latency data paths and control logic.
- Develop mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Define interfaces between UALink and other SoC or interconnect components.
- Develop and review SystemVerilog RTL.
- Drive design optimization for performance, power, area, and latency.
- Debug complex simulation and integration issues and provide technical leadership.
Requirements
- Strong experience in RTL and microarchitecture development.
- Experience with high-speed interconnects and/or coherent fabrics.
- Strong understanding of computer architecture, networking concepts, and data movement.
- Proficiency in SystemVerilog/Verilog.
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Good to have
- Direct UALink experience.
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
- Experience in AI/accelerator or high-performance compute systems.
Who should apply
This role suits experienced semiconductor professionals with a strong background in high-performance interconnect and SoC or IP design. Ideal candidates will possess extensive hands-on experience in RTL and microarchitecture development, proficiency in SystemVerilog, and a solid understanding of computer architecture. Candidates who have previously worked with high-speed protocols and high-performance compute systems will find this opportunity a strong fit for their skill set.
Frequently asked questions
What is the location of the Principal Logic Design Engineer – UALink IP/Subsystem role at Astera Labs?
The Principal Logic Design Engineer – UALink IP/Subsystem position is located in Bengaluru, Karnataka, India.
What experience level is required for the Principal Logic Design Engineer position at Astera Labs?
Astera Labs requires 10–15 years of experience for the Principal Logic Design Engineer – UALink IP/Subsystem role.
What core skills are needed for the Principal Logic Design Engineer – UALink IP/Subsystem job at Astera Labs?
Key requirements include strong RTL and microarchitecture development experience, high-speed interconnects or coherent fabrics background, SystemVerilog proficiency, and understanding of CDC and hardware design methodologies.
What does Astera Labs do as a company?
Astera Labs provides rack-scale AI infrastructure through connectivity solutions that unify diverse components into cohesive systems for end-to-end scale-up and scale-out connectivity.
Rojgar Point lists this job for information. Always apply on the official company page and never pay anyone for a job.