Senior Principal Physical Design Engineer

About this job

Astera Labs in Bengaluru is hiring a Senior Principal Physical Design Engineer for its rack-scale AI infrastructure team. Astera Labs develops purpose-built connectivity solutions, combining semiconductor technologies like PCIe, CXL, and Ethernet with the COSMOS software suite to create scalable AI and cloud infrastructure systems. In this role, you will work on advanced silicon products for server, storage, and networking applications. A normal day involves driving physical design activities, managing backend tools and methodologies for advanced process nodes, handling synthesis, place and route, clock tree synthesis, and timing closure, and collaborating with cross-functional teams and IP vendors to bring complex designs to production while maintaining an entrepreneurial and customer-focused attitude.

Responsibilities

• Manage full chip or block level ownership from architecture to GDSII for complex designs.
• Drive synthesis, place and route, CTS, extraction, timing analysis, and physical verification.
• Execute synthesis, timing closure, and formal equivalence verification at block and full-chip levels.
• Utilize Cadence and/or Synopsys physical design tools and flows for advanced technology nodes.
• Work alongside IP vendors for both RTL and hard-mac blocks.
• Apply DFT tools and techniques during the design cycle.
• Write scripts using Python or Perl to support workflow automation and efficiency.

Requirements

• Bachelor's degree in Electrical Engineering or Computer Science.
• At least 6 years of experience supporting or developing complex SoC or silicon products.
• Hands-on expertise in backend tools for technologies of 16nm or less.
• Working knowledge of System Verilog and Verilog.
• Ability to work with minimal guidance and prioritize dynamic tasks effectively.

Good to have

• Master's degree in Electrical Engineering or Computer Science.
• Knowledge of design for test, stuck-at, and transition scan test insertion.
• Familiarity with DFT test coverage and debugging processes.
• Experience with ECO methodologies and related tools.
• Experience with sub-7nm process technologies.

Who should apply

This role suits experienced engineering professionals with a strong background in electrical engineering and a history of developing complex SoC or silicon products for server, storage, or networking. Candidates should have substantial hands-on expertise in physical design methodologies for advanced nodes. Freshers cannot apply as the position requires at least six years of relevant experience. Ideal applicants display an entrepreneurial spirit, strong multitasking capabilities, and a professional attitude toward customer-centric execution.

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