Tech Lead, STA

About this job

Astera Labs is looking for a Tech Lead, STA based in Hyderabad to manage top-level timing closure and signoff for advanced connectivity silicon. Astera Labs develops rack-scale AI infrastructure through connectivity solutions, using semiconductor-based technologies and the COSMOS software suite to build scalable AI systems. In a normal day, the Tech Lead manages full-chip static timing analysis strategy across advanced process nodes, collaborates with physical design, RTL, DFT, and CAD teams, solves complex timing violations, and mentors team members. This technical leadership position offers the opportunity to drive timing convergence from early floorplan through tapeout while shaping the company's STA methodology and automation flows for modern AI connectivity platforms.

Responsibilities

• Manage end-to-end top-level STA signoff across multiple modes, corners, and operating conditions for AI connectivity SoCs.
• Drive timing convergence on advanced process nodes from early floorplan through tapeout.
• Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing timing violations at the chip level.
• Define STA methodology, constraints strategy, and signoff criteria across the organization.
• Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools.
• Partner with physical design, RTL, DFT, CAD, and package teams to guide timing-aware design choices.
• Mentor STA engineers, review timing reports and ECOs, and contribute to methodology improvements.

Requirements

• 6-14 years of hands-on experience in Static Timing Analysis on complex ASIC or SoC designs.
• Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below).
• Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development.
• Strong understanding of clocking architectures, clock-domain crossing, OCV/AOCV/POCV, crosstalk, and IR-aware timing.
• Proficiency in scripting languages such as Tcl, Python, or Perl for automation and report analysis.
• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.

Good to have

• Master's degree in Electrical Engineering or a related field.
• Experience with high-speed connectivity SoCs including PCIe Gen 6/7, CXL, UALink, or Ethernet.
• Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions.
• Experience with low-power signoff, multi-voltage domains, and DVFS timing implications.
• Strong cross-functional collaboration and mentorship skills in a fast-paced product environment.

Who should apply

This role is well-suited for experienced semiconductor professionals with a strong background in static timing analysis and advanced node tapeouts. Candidates who enjoy cross-functional leadership, technical mentorship, and driving full-chip timing closure for cutting-edge AI connectivity chips will thrive here. The posting does not state that freshers can apply, as a minimum of 6 years of hands-on STA experience is required.

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