Lead Logic Design Engineer

About this job

Astera Labs is seeking a Lead Logic Design Engineer to join the team in Bengaluru, Karnataka, to work on purpose-built connectivity solutions for rack-scale AI infrastructure. The company integrates advanced semiconductor-based technologies with its COSMOS software suite to help organizations build flexible, cohesive AI systems. In this role, you will take technical ownership of complex IPs and subsystems from architecture through to silicon bring-up. A normal day in this position involves translating system requirements into robust hardware, developing and reviewing RTL using SystemVerilog or Verilog, optimizing designs for performance, power, and area, and collaborating closely with verification, SoC integration, and physical design teams. You will also lead technical reviews, mentor senior engineers, and support post-silicon debug and root-cause analysis.

Responsibilities

• Lead RTL and microarchitecture development for complex connectivity IP and subsystems.
• Translate system requirements and specifications into reliable hardware architecture.
• Design scalable, high-performance logic for controllers and subsystems.
• Develop and review RTL using SystemVerilog and Verilog.
• Drive optimizations for latency, performance, area, and power.
• Collaborate with verification teams to shape strategies and debug complex design failures.
• Work alongside SoC integration and physical design teams for successful implementation.
• Support post-silicon debug and root-cause analysis alongside leading technical reviews.

Requirements

• Extensive background in complex connectivity IPs such as PCIe, UALink, Ethernet, CXL, and UCIe.
• Strong hands-on RTL design experience utilizing SystemVerilog or Verilog.
• Deep knowledge and understanding of PCIe architecture and protocols.
• Solid grasp of high-speed data paths, FIFOs, flow control, arbitration, and error handling.
• Familiarity with simulation, synthesis, lint, CDC, and timing considerations.
• Strong problem-solving and debugging skills.

Good to have

• Experience working in switching silicon.
• Experience managing the complete product lifecycle from concept to silicon production.

Who should apply

This role is ideal for experienced hardware professionals with a deep background in micro-architecture and RTL design who want to take technical ownership of connectivity IPs. Candidates should have a strong track record in complex connectivity protocols like PCIe and CXL. Because the position requires leadership and mentoring of senior engineers, it suits professionals ready to guide teams through full product lifecycles. Freshers cannot apply as 6-10 years of experience is required.

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