Lead Logic Design Engineer
About this job
Astera Labs is hiring a Lead Logic Design Engineer in Bengaluru to work on rack-scale AI infrastructure and connectivity solutions. The company builds purpose-built connectivity products that integrate advanced semiconductor technologies with its COSMOS software suite to help organizations scale modern AI systems. In this role, you will lead the RTL and microarchitecture development for UALink-based IP and subsystems. A normal day in this position involves translating protocol requirements into detailed microarchitectures, designing high-performance control and data-path logic, developing SystemVerilog RTL, and optimizing designs for performance, power, and latency. You will also collaborate closely with verification, SoC integration, and physical design teams, debug complex functional issues, review technical work, and mentor other engineers to support successful silicon deployment.
Responsibilities
- Lead UALink IP and subsystem RTL development and microarchitecture creation
- Design high-performance control and data-path logic focusing on data movement and flow control
- Develop and review SystemVerilog RTL while driving optimization for power, area, and latency
- Work on buffering, arbitration, ordering, and error handling mechanisms
- Collaborate with verification, SoC integration, and physical design teams
- Debug complex functional and integration issues and support silicon debug
- Review RTL and mentor fellow engineers on the team
Requirements
- 6–10 years of relevant experience
- Strong background in RTL and microarchitecture development
- Experience working with high-speed interconnects
- Solid understanding of data movement, flow control, arbitration, and buffering
- Excellent skills in SystemVerilog or Verilog
- Experience with CDC, lint, synthesis, and timing
- Strong debugging abilities and demonstrated technical leadership skills
Good to have
- Direct experience with UALink
- Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies
- Experience with AI, accelerator, or high-performance compute SoCs
Who should apply
This role suits experienced engineering professionals with six to ten years of background in logic design, RTL development, and high-speed interconnects. Candidates who have a strong grasp of SystemVerilog, data movement logic, and microarchitecture design will find this position a great fit. If you have experience mentoring engineers and driving technical leadership in high-performance computing or AI infrastructure teams at Astera Labs, you are encouraged to apply.
Frequently asked questions
What is the location for the Lead Logic Design Engineer role at Astera Labs?
The Lead Logic Design Engineer position is based in Bengaluru, Karnataka, India.
What experience is required to apply for the Lead Logic Design Engineer position at Astera Labs?
Candidates need 6 to 10 years of experience in RTL, microarchitecture, and high-speed interconnects.
What will I do daily as a Lead Logic Design Engineer at Astera Labs?
You will lead UALink IP RTL development, design control and data-path logic, optimize performance and power, and collaborate with verification and physical design teams.
Are there any preferred technical skills for the Astera Labs Lead Logic Design Engineer role?
Preferred skills include direct UALink experience, familiarity with PCIe, CXL, Ethernet, or CCIX, and background in AI or high-performance compute SoCs.
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